Amirmahdi Joudi

Amirmahdi Joudi

PhD Student in Electrical and Electronics Engineering. Researching interesting things in Embedded-BCI.

Brief Bio

Amirmahdi Joudi is a first-year PhD student in EDEE at EPFL, working in the Integrated Neurotechnologies Lab (INL) under the supervision of Professor Mahsa Shoaran. He holds both a Master’s and a Bachelor’s degree in Electrical Engineering (Digital Systems) from the University of Tehran. His research focuses on integrated brain–computer interface (BCI) systems, with an emphasis on neural decoding for implantable platforms. He works across digital and mixed-signal hardware design to develop efficient, next-generation BCI technologies.

Research Interests

I’m interested in digital and mixed-signal circuit design. In this field, I focus on algorithms, optimize them for particular applications, and create efficient hardware. This process requires a system-level perspective to determine which algorithmic choices will support efficient hardware design down to the transistor level. It takes circuits and software skills built through years of research and hands-on experience. I believe that an expert in hardware design gains broad knowledge across many fields and always has the opportunity to explore new areas and apply this knowledge in hardware to achieve success. Currently, I am conducting research on implantable BCI systems for speech decoding, which require low-power, low-latency, and reliable performance. My work spans very large ML and neural network models to decode neural activity into meaningful phonemes and words, helping people who suffer from impaired communication abilities.

Projects

  • Continuos Wavelet Transform (CWT) Hardware Design:
    • CWT implementation in 65 nm technology using Verilog.
    • The module supports 32 or 64 channels with 10 or 5 configurable frequencies.
    • It allows up to 256 filter taps and employs resource sharing to optimize utilization.
    • The design operates at 10 MHz with a total power consumption of approximately 2.5 mW.
  • PIES-BCI: Project for Implementation of an Embedded System for Brain Computer Interface:
    • For my master’s thesis, I developed an embedded system for a Brain–Computer Interface (BCI), specifically a P300 Speller that integrated an IIR filter, synchronized averaging, and a linear classifier. The project involved several key challenges, including area and power optimization, maintaining high accuracy in DNN design, and implementing precise DSP filters.
    • I also focused on system reconfigurability. Existing chips in this field were often highly customized, which became limiting when requirements evolved. To address this, I introduced configurable elements, such as adjusting the number of second-order sections (SOS) in the IIR filter. In addition, I created a high-level framework to support future extensions, enabling users to design their systems at an abstract level and compile them directly into hardware.
  • HIRMA: High-performance Implementation for RISC-V Microcontroller Applications:
    • This project presents the design and implementation of a fully synthesizable 32-bit microcontroller in 180nm CMOS technology, covering the complete flow from RTL development to ASIC layout.
    • The microcontroller, named HIRMA, is built around an open-source RISC-V IM processor connected through customized buses for internal communication. It integrates a 4 kB SRAM, an SPI flash controller for loading instructions from external flash into SRAM, a UART transmitter/receiver, a 32-bit timer, and support for external off-chip accelerators. All peripherals are managed by the RISC-V core, and an SPI master interface is used to program the on-chip SRAM.
    • The project includes the full development flow—from architectural design to final layout generation and introduces an affordable, easy-to-implement platform for post-manufacturing testing.
    • The finalized microcontroller achieves a total power consumption of 10.7091 mW at 50 MHz and occupies a compact 1 mm × 2 mm area, including the I/O pad frame.
      • 2023 IEEE East-West Design & Test Symposium (EWDTS)
      GitHub
  • An Integrated Framework for Aging Analysis Based on an Age-Aware Cell Library:
    • Designers are often compelled to make compromises to ensure reliable functionality as transistors age, which can hinder efficiency. Conventional aging analysis tools are slow and impractical for complex circuits. Thus, this study introduces a gate-level back-annotation of aging characteristics that improves simulation efficiency and retains accuracy at an acceptable level.
    • This method is used in a uniform framework that brings in aging considerations in an event-based simulation environment and automates the extraction of the required information to fit in the mentioned environment. This results in the calibration of simulation units defined as gate models for bridging device-level to system-level analysis. Considering today’s digital design complexities, this work incorporates the conventional aging analysis into an event-based simulator, which provides much faster analysis time.
    • This approach achieves an average speedup of 7.12 versus HSPICE and maintains accuracy with an average pessimism of 0.29%, making it a practical environment for analyzing aging effects on reliability.
      • 2025 IEEE European Test Symposium (ETS)
  • AFTAB Optimization:
    • Delay and power optimization of a multi-cycle RISC-V processor named AFTAB, performed using the open-source EDA tool QFlow. This work was completed as an undergraduate project.
  • RISCV Development:
    • A pipelined RISC-V processor supporting multiple extensions, along with interrupt and exception handling. The current implementation provides an RV32I core with machine-mode support and precise interrupt and exception handling.
      • GitHub
  • MIPS Development:
    • A pipelined MIPS processor supporting multiple extensions, along with a 2-way superscalar version.
      • GitHub
  • Object-Oriented Modeling of Electronic Systems:
    • In a course of the same name, the concepts of ESL and object-oriented modeling of electronic systems were covered. Key topics included Design Space Exploration (DSE), Instruction Set Simulation (ISS), Bus Functional Modeling, RTL design, concurrency in digital logic design simulators, compilation, C++, SystemC, and SystemC-AMS modeling.
      • GitHub
  • Deep Learning and Neural Networks:
    • In this course, a series of projects were completed, each implementing key papers in the fields of deep learning and neural networks. These projects covered important concepts and practical techniques discussed throughout the course. Concepts from simple ones like mcclotchPitts to advanced ones like GANs were covered. A teammate and I collaborated on all of these works.
      • GitHub
  • VHDL Description of Intel 8085 Microprocessor:
    • A general overview of the Intel 8085 datapath is available online, and this reference, along with the official datasheet, was used to design both the datapath and the controller. The design is implemented in Huffman style.
      • GitHub
  • VHDL Description of a simple pipeline MLP:
    • The Iris MLP is used for classifying Iris flower species: Setosa, Versicolor, and Virginica. In this project, a neural network is described in VHDL using extracted coefficients, and the dataset is applied to the network. The resulting outputs are then analyzed.
      • GitHub