Amirmahdi Joudi
About me
I'm Amirmahdi, and I'm completing the final year of my master’s program in Electrical Engineering with a focus on Digital Electronic Systems at the University of Tehran, Iran. Additionally, I hold a bachelor’s degree in Electrical Engineering with a focus on Digital Systems from the University of Tehran. My experience researching hardware design and optimization has helped me develop the skills necessary for a full-time research position. I am familiar with various aspects of hardware design, VLSI, and embedded Brain-Computer Interface systems.Â
On the technical side, I have worked on Digital Logic Design since 2020. I have studied courses and worked at different levels, including high and system-level design, RTL design, verification, test and testability, and low-power design. My current focuses are on computer architecture, hardware for machine learning, and, these days, embedded brain-computer interfaces (BCI). I find designing hardware for machine learning, digital signal processing, and brain-computer interfaces interesting.Â
Documents                                                    Â
Resume [PDF]
Updated March. 2025
Interests                                                    Â
I'm interested in digital logic and hardware design. Researchers in this field focus on algorithms, optimize them for particular applications, and create efficient hardware. This process requires a system-level perspective to determine which algorithmic choices will support efficient hardware design down to the transistor level. It takes hardware and software skills built through years of research and hands-on experience. I believe that an expert in hardware design gains broad knowledge across many fields and always has the opportunity to explore new areas and apply this knowledge in hardware to find success.
Experiences: Skills and Learnings
Logic Design
CAD Lab
2020 - Now
I work on digital logic design, from ESL to GDS. I work on ESL design, processors, accelerators, SoC frameworks, EDA tools, post-manufacturing testing, and testers. My primary interests in logic design include hardware for machine learning (ML), artificial intelligence (AI) hardware, and accelerator design. As part of my graduate thesis, I am working on a BCI-based System-on-Chip (SoC) design. I am designing an embedded system that can perform BCI applications, including filtering, P300 ERP, and Deep Neural Network (DNN) in BCI, and I am also preparing an interface with a computer for signal capture and processing.Â
Verilog/SystemVerilog/VHDL
SystemC/SystemC-AMS
C/C++
Modelsim/QuestaSim
Quartus/Vivado
Cadence: Innovus - Virtuoso
Synopsys: Design Compiler - Hspice/Hspice-MOSRA
Calibre
Qflow toolchain: Yosys
Python: pytorch/tensorflow/keras
EEG signals classification
BCI: Brain-Computer Interface
I have also become familiar with some other concepts throughout my courses; some of these courses and concepts are:
Undergraduate:
Advanced Programming (C++)
Artificial Intelligence (search algorithms, CSP, Genetic Algorithm, Naive Bayes, Decision Trees, Propositional and First-order Logic)
Core-based Embedded Systems Design (GEM5, ASIP and openasip, VLIW, OOO Processors, Vector Processors, CUDA Programming)
Digital Electronic Circuits (FET, Static CMOS, Logic Family, Adders, Sequential Logic Circuit, Fabrication, Stick Diagrams, Design Rules, Packaging)
Electronic System Level Design (HLS, CatapultC, MATLAB HDL Coder, CHISEL)
FPGA-based Embedded Systems Design (ALTERA FPGAs, Timing Analysis)
Introduction to Digital System Design Algorithms (Algorithms, Data Structure, Design Cycle, Optimization)
Object-Oriented Modeling of Electronic Circuits (SystemC, SystemC-AMS)
Operating System (XV6)
Parallel Programming (SIMD, OpenMP, POSIX, Intel Parallel Studio, CUDA)
Graduate:
Advanced Computer Architecture (Pipeline, Memory Hierarchy, Superscalar, VLIW, Advanced Cache, Branch Prediction, Address Translation and Protection, Vector Processor, GPU, SIMD, Multithreading)
Advanced VLSI (MOS Device, Interconnects, Combinational Logic, Sequential Logic, Implementation Methodologies, FPGAs, Designing Arithmetic Building Blocks, Semiconductor Memories, Manufacturing Process, Packaging)
Computer Arithmetic (Conventional and Unconventional Numbering Systems, Adders, Signed Digit Adders, Multi Operand Addition, Multiplication, Division, Floating Points)
Fault-Tolerant Systems (Hardware Redundancy, Information Redundancy, Time Redundancy, Evaluation Techniques, Fault Tolerant Networks, Fault-Tolerant Software)
Neural Network (Autoencoders, CNNs, RCNN, RNN, Transformers, GANs)
Test and Testability (Fault Detection, TPG, PODEM, SCAN, BIST, STUMPS, JTAG, Memory Testing)
Verification (Formal Verification)
VHDL (VHDL, SystemC)
R&D Engineer
MEHBANG [Website]
2021 - 2023
To increase my basic engineering knowledge, I experienced a 3-month internship and a 15-month job at MEHBANG, a big holding with different products and brands. During my internship, I worked in QUBY, a vending machine that is now popular in Iran. I designed a Raspberry Pi-based tester for the product line at the factory, featuring a graphical user interface (GUI) to simplify its use. Then, I became a member of the embedded programming department and worked on various products, including industrial inverters and elevator control panels. I was an ARM programmer and tester in this department. I learned to work with multiple measurement equipment. This was an excellent experience for me, as I learned many skills.
ARM microcontrollers
PCB Design: Altium Designer
PCB Montage
Raspberry Pi
GUI: Python KIVY
Current Projects
Currently, I am involved in different projects. They are study and implementation groups.Â
In this project, we study open-source tools and microcontroller design.
In this project, we are designing an embedded system.
In my thesis project, I am working on embedded BCI.
I was also involved in several other projects during recent months that resulted in the publication of papers. The published papers are all parts of these similar projects.
Publications
HIRMA: High-Performance Implementation for RISC-V Microcontroller Applications
2023 IEEE East-West Design & Test Symposium (EWDTS)
2023
In this paper a complete flow, from design toward ASIC implementation of a fully synthesizable 32-bit microcontroller in 180nm CMOS technology is presented. This microcontroller, referred to as HIRMA, features the opensource RISC-V IM processor mounted through customized busses for communication processes. The microcontroller contains a 4kB-SRAM, SPI flash controller for inserting instructions from external flash to SRAM, a UART transmitter and receiver module, a 32-bit timer, and capability of external off-chip accelerators. All peripherals are controlled by a RISCV processor, and an SPI master interface that is used for programming the SRAM in the system. In this paper, we exhibit the design of our proposed microcontroller and present our design flow from Register-Transfer Level design to generating an ASIC layout. An affordable and easy to implement platform for post-manufacturing testing is also introduced. A total power density is reported as 10.7091mW in 50 MHz and the area for this RISC-V microcontroller has a reduced footprint of 1mm × 2mm including I/O pad modules.Â
An Integrated Framework for Creating System-Level Compatible Age-Aware Library CellsÂ
Admitted to ETS 2025
2024
Designers are often compelled to make compromises to ensure reliable functionality as transistors age, which can hinder efficiency. Conventional aging analysis tools are slow and impractical for complex circuits. Thus, this study introduces a gate-level back-annotation of aging characteristics that improves simulation efficiency and retains accuracy at an acceptable level. This method is used in a uniform framework that brings in aging considerations in an event-based simulation environment and automates the extraction of the required information to fit in the mentioned environment. This results in the calibration of simulation units defined as gate models for bridging device-level to system-level analysis. Considering today’s digital design complexities, this work incorporates the conventional aging analysis into an event-based simulator, which provides much faster analysis time. This approach achieves an average speedup of 7.12 versus HSPICE and maintains accuracy with an average pessimism of 0.29%, making it a practical environment for analyzing aging effects on reliabilityÂ
News                                                    Â
I am selected for E3 (EPFL Excellence in Engineering) program, a prestigious three-month internship in the Integrated Neurotechnology Lab under the supervision of Professor Mahsa Shoaran, which I will attend before the upcoming fall semester. (12/19/2024)
💡 Projects
I explained some of my projects with details including codes, papers, and videos here.